A significant cost in electronics manufacturing is testing. Individual components must be tested and assembled systems must be tested. It is common to include additional circuitry to facilitate testing. Circuitry for testing is typically used in a special test mode, often under static conditions. That is, the test circuitry is used to sequence an integrated circuit through states specifically for testing and the results are monitored with the system clock slowed or paused. It is also common to include circuitry to capture the state of input/output signals (called boundary scan testing). A commonly used standard for such circuitry is IEEE Std. 1149.1-1990, IEEE Standard Test Access Port and Boundary-Scan Architecture, available from The Institute of Electrical and Electronic Engineers, Inc., 345 East 47th Street, New York, N.Y. 10017-2394. IEEE Std. 1149.1 defines a standard serial interface through which test instructions and test data are communicated. The technique involves the inclusion of a shift-register stage adjacent to each component pin of interest so that signals at component boundaries can be controlled and observed. The special shift-registers and test instructions can be used in isolated component testing and in testing individual components assembled into larger systems.
The IEEE 1149.1 standard defines a Test Access Port (TAP). The standard also includes specification of a test clock (TCK). Typically, testing compatible with the IEEE 1149.1 standard requires synchronization of the test clock TCK and internal component clocks. Generally, only boundary signals are captured. Internal component states are generally not captured unless the component is in a special test mode in which internal states are propagated to the boundary just for testing. There is a need for testing that captures internal logic states at the operating frequency of the device. There is a need for capturing internal logic states at the operating frequency of the device and reading those captured internal states using industry standard boundary scan testing ports. There is a need for a test system that non-destructively captures internal logic states while the device is operating at normal frequency and that permits reading of the captured states while the device continues to operate.